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1.35v ddr3l sdram MT41K512M4 C 64 meg x 4 x 8 banks mt41k256m8 C 32 meg x 8 x 8 banks mt41k128m16 C 16 meg x 16 x 8 banks description ddr3l sdram (1.35v) is a low voltage version of the ddr3 sdram (1.5v). unless stated otherwise, ddr3l sdram meet the functional and timing specifications listed in the equivalent density ddr3 sdram data sheet located on www.micron.com. features ? v dd = v ddq = 1.35v (1.283C1.45v) ? backward-compatible to v dd = v ddq = 1.5v 0.075v ? differential bidirectional data strobe ? 8 n -bit prefetch architecture ? differential clock inputs (ck, ck#) ? 8 internal banks ? nominal and dynamic on-die termination (odt) for data, strobe, and mask signals ? programmable cas (read) latency (cl) ? programmable posted cas additive latency (al) ? programmable cas (write) latency (cwl) ? fixed burst length (bl) of 8 and burst chop (bc) of 4 (via the mode register set [mrs]) ? selectable bc4 or bl8 on-the-fly (otf) ? self refresh mode ? t c of 0c to +95c C 64ms, 8192-cycle refresh at 0c to +85c C 32ms at +85c to +95c ? self refresh temperature (srt) ? automatic self refresh (asr) ? write leveling ? multipurpose register ? output driver calibration options marking ? configuration C 512 meg x 4 512m4 C 256 meg x 8 256m8 C 128 meg x 16 128m16 ? fbga package (pb-free) C x4, x8 C 78-ball (8mm x 10.5mm) rev. h, m, k da C 78-ball fbga (9mm x 11.5mm) rev. d hx ? fbga package (pb-free) C x16 C 96-ball fbga (9mm x 14mm) rev. d ha C 96-ball fbga (8mm x 14mm) rev. k jt ? timing C cycle time C 1.25ns @ cl = 11 (ddr3-1600) -125 C 1.5ns @ cl = 9 (ddr3-1333) -15e C 1.875ns @ cl = 7 (ddr3-1066) -187e ? revision :d/ :h/ :k/ : m table 1: key timing parameters speed grade data rate (mt/s) target t rcd- t rp-cl t rcd (ns) t rp (ns) cl (ns) -125 1, 2 1600 11-11-11 13.75 13.75 13.75 -15e 1 1333 9-9-9 13.5 13.5 13.5 -187e 1066 7-7-7 13.1 13.1 13.1 notes: 1. backward compatible to 1066, cl = 7 (-187e). 2. backward compatible to 1333, cl = 9 (-15e). 2gb: x4, x8, x16 ddr3l sdram description pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice. www.datasheet.co.kr datasheet pdf - http://www..net/
table 2: addressing parameter 512 meg x 4 256 meg x 8 128 meg x 16 configuration 64 meg x 4 x 8 banks 32 meg x 8 x 8 banks 16 meg x 16 x 8 banks refresh count 8k 8k 8k row address 32k a[14:0] 32k a[14:0] 16k a[13:0] bank address 8 ba[2:0] 8 ba[2:0] 8 ba[2:0] column address 2k a[11, 9:0] 1k a[9:0] 1k a[9:0] 2gb: x4, x8, x16 ddr3l sdram description pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
ball assignments and descriptions figure 1: 78-ball fbga C x4, x8 ball assignments (top view) 1 2 3 4 6 7 8 9 5 v ss v ss v ddq v ssq v refdq nc odt nc v ss v dd v ss v dd v ss v dd v ssq dq2 nf, dq6 v ddq v ss v dd cs# ba0 a3 a5 a7 reset# nc dq0 dqs dqs# nf, dq4 ras# cas# we# ba2 a0 a2 a9 a13 nf, nf/tdqs# dm, dm/tdqs dq1 v dd nf, dq7 ck ck# a10/ap nc a12/bc# a1 a11 a14 v dd v ddq v ssq v ssq v ddq nc cke nc v ss v dd v ss v dd v ss v ss v ssq dq3 v ss nf, dq5 v ss v dd zq v refca ba1 a4 a6 a8 a b c d e f g h j k l m n notes: 1. ball descriptions listed in table 3 (page 5) are listed as x4, x8 if unique; otherwise, x4 and x8 are the same. 2. a comma separates the configuration; a slash defines a selectable function. example: d7 = nf, nf/tdqs#. nf applies to the x4 configuration only. nf/tdqs# applies to the x8 configuration onlyselectable between nf or tdqs# via mrs (symbols are de- fined in table 3). 2gb: x4, x8, x16 ddr3l sdram ball assignments and descriptions pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 2: 96-ball fbga C x16 ball assignments (top view) 1 2 3 4 6 7 8 9 5 a b c d e f g h j k l m n p r t v ddq v ssq v ddq v ssq v ss v ddq v ssq v refdq nc odt nc v ss v dd v ss v dd v ss dq13 v dd dq11 v ddq v ssq dq2 dq6 v ddq v ss v dd cs# ba0 a3 a5 a7 reset# dq15 v ss dq9 udm dq0 ldqs ldqs# dq4 ras# cas# we# ba2 a0 a2 a9 a13 dq12 udqs# udqs dq8 ldm dq1 v dd dq7 ck ck# a10/ap nc a12/bc# a1 a11 nc v ddq dq14 dq10 v ssq v ssq dq3 v ss dq5 v ss v dd zq v refca ba1 a4 a6 a8 v ss v ssq v ddq v dd v ddq v ssq v ssq v ddq nc cke nc v ss v dd v ss v dd v ss notes: 1. ball descriptions listed in table 4 (page 7) are listed as x16. 2gb: x4, x8, x16 ddr3l sdram ball assignments and descriptions pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
2. a comma separates the configuration; a slash defines a selectable function. table 3: 78-ball fbga C x4, x8 ball descriptions symbol type description a[14:13], a12/bc#, a11, a10/ap, a[9:0] input address inputs: provide the row address for activate commands, and the column address and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge com- mand determines whether the precharge applies to one bank (a10 low, bank selected by ba[2:0]) or all banks (a10 high). the address inputs also provide the op-code during a load mode command. address inputs are referenced to v refca . a12/bc#: when enabled in the mode register (mr), a12 is sampled during read and write commands to deter- mine whether burst chop (on-the-fly) will be performed (high = bl8 or no burst chop, low = bc4 burst chop). ba[2:0] input bank address inputs: ba[2:0] define the bank to which an activate, read, write, or precharge command is being applied. ba[2:0] define which mode register (mr0, mr1, mr2, or mr3) is loaded during the load mode command. ba[2:0] are referenced to v refca . ck, ck# input clock: ck and ck# are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and the negative edge of ck#. out- put data strobe (dqs, dqs#) is referenced to the crossings of ck and ck#. cke input clock enable: cke enables (registered high) and disables (registered low) internal cir- cuitry and clocks on the dram. the specific circuitry that is enabled/disabled is depend- ent upon the ddr3 sdram configuration and operating mode. taking cke low pro- vides precharge power-down and self refresh operations (all banks idle) or active power-down (row active in any bank). cke is synchronous for power-down entry and exit and for self refresh entry. cke is asynchronous for self refresh exit. input buffers (exclud- ing ck, ck#, cke, reset#, and odt) are disabled during power-down. input buffers (ex- cluding cke and reset#) are disabled during self refresh. cke is referenced to v refca . cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs# is registered high. cs# provides for exter- nal rank selection on systems with multiple ranks. cs# is considered part of the command code. cs# is referenced to v refca . dm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high along with the input data during a write access. although the dm ball is input-only, the dm loading is designed to match that of the dq and dqs balls. dm is referenced to v refdq . dm has an optional use as tdqs on the x8 device. odt input on-die termination: odt enables (registered high) and disables (registered low) ter- mination resistance internal to the ddr3 sdram. when enabled in normal operation, odt is only applied to each of the following balls: dq[7:0], dqs, dqs#, and dm for the x8; dq[3:0], dqs, dqs#, and dm for the x4. the odt input is ignored if disabled via the load mode command. odt is referenced to v refca . ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered and are referenced to v refca . reset# input reset: reset# is an active low cmos input referenced to v ss . the reset# input receiver is a cmos input defined as a rail-to-rail signal with dc high 0.8 v ddq and dc low 0.2 v ddq . reset# assertion and deassertion are asynchronous. 2gb: x4, x8, x16 ddr3l sdram ball assignments and descriptions pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 3: 78-ball fbga C x4, x8 ball descriptions (continued) symbol type description dq[3:0] i/o data input/output: bidirectional data bus for the x4 configuration. dq[3:0] are refer- enced to v refdq . dq[7:0] i/o data input/output: bidirectional data bus for the x8 configuration. dq[7:0] are refer- enced to v refdq . dqs, dqs# i/o data strobe: output with read data. edge-aligned with read data. input with write da- ta. center-aligned to write data. tdqs, tdqs# i/o termination data strobe: applies to the x8 configuration only. when tdqs is enabled, dm is disabled, and the tdqs and tdqs# balls provide termination resistance. v dd supply power supply: 1.35v, 1.283C1.45v operational; compatible to 1.5v operation. v ddq supply dq power supply: 1.35v, 1.283C1.45v operational; compatible with 1.5v operation. v refca supply reference voltage for control, command, and address: v refca must be maintained at all times (including self refresh) for proper device operation. v refdq supply reference voltage for data: v refdq must be maintained at all times (including self re- fresh) for proper device operation. v ss supply ground. v ssq supply dq ground: isolated on the device for improved noise immunity. zq reference external reference ball for output drive calibration: this ball is tied to an external 240 resistor (r zq ), which is tied to v ssq . nc C no connect: these balls should be left unconnected (the ball has no connection to the dram or to other balls). nf C no function: when configured as a x4 device, these balls are nf. when configured as a x8 device, these balls are defined as tdqs#, dq[7:4]. 2gb: x4, x8, x16 ddr3l sdram ball assignments and descriptions pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 4: 96-ball fbga C x16 ball descriptions symbol type description a13, a12/bc#, a11, a10/ap, a[9:0] input address inputs: provide the row address for activate commands, and the column address and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge com- mand determines whether the precharge applies to one bank (a10 low, bank selected by ba[2:0]) or all banks (a10 high). the address inputs also provide the op-code during a load mode command. address inputs are referenced to v refca . a12/bc#: when enabled in the mode register (mr), a12 is sampled during read and write commands to deter- mine whether burst chop (on-the-fly) will be performed (high = bl8 or no burst chop, low = bc4 burst chop). ba[2:0] input bank address inputs: ba[2:0] define the bank to which an activate, read, write, or precharge command is being applied. ba[2:0] define which mode register (mr0, mr1, mr2, or mr3) is loaded during the load mode command. ba[2:0] are referenced to v refca . ck, ck# input clock: ck and ck# are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and the negative edge of ck#. out- put data strobe (ldqs, ldqs#, udqs, udqs#) is referenced to the crossings of ck and ck#. cke input clock enable: cke enables (registered high) and disables (registered low) internal cir- cuitry and clocks on the dram. the specific circuitry that is enabled/disabled is depend- ent upon the ddr3 sdram configuration and operating mode. taking cke low pro- vides precharge power-down and self refresh operations (all banks idle) or active power-down (row active in any bank). cke is synchronous for power-down entry and exit and for self refresh entry. cke is asynchronous for self refresh exit. input buffers (exclud- ing ck, ck#, cke, reset#, and odt) are disabled during power-down. input buffers (ex- cluding cke and reset#) are disabled during self refresh. cke is referenced to v refca . cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs# is registered high. cs# provides for exter- nal rank selection on systems with multiple ranks. cs# is considered part of the command code. cs# is referenced to v refca . ldm input input data mask: ldm is a lower-byte, input mask signal for write data. lower-byte in- put data is masked when ldm is sampled high along with the input data during a write access. although the ldm ball is input-only, the ldm loading is designed to match that of the dq and ldqs balls. ldm is referenced to v refdq . odt input on-die termination: odt enables (registered high) and disables (registered low) ter- mination resistance internal to the ddr3 sdram. when enabled in normal operation, odt is only applied to each of the following balls: dq[15:0], ldqs, ldqs#, udqs, udqs#, ldm, and udm for the x16. the odt input is ignored if disabled via the load mode command. odt is referenced to v refca . ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered and are referenced to v refca . reset# input reset: reset# is an active low cmos input referenced to v ss . the reset# input receiver is a cmos input defined as a rail-to-rail signal with dc high 0.8 v ddq and dc low 0.2 v ddq . reset# assertion and deassertion are asynchronous. 2gb: x4, x8, x16 ddr3l sdram ball assignments and descriptions pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 4: 96-ball fbga C x16 ball descriptions (continued) symbol type description udm input input data mask: udm is an upper-byte, input mask signal for write data. upper-byte input data is masked when udm is sampled high along with the input data during a write access. although the udm ball is input-only, the udm loading is designed to match that of the dq and udqs balls. udm is referenced to v refdq . dq[7:0] i/o data input/output: lower byte of bidirectional data bus for the x16 configuration. dq[7:0] are referenced to v refdq . dq[15:8] i/o data input/output: upper byte of bidirectional data bus for the x16 configuration. dq[15:8] are referenced to v refdq . ldqs, ldqs# i/o lower byte data strobe: output with read data. edge-aligned with read data. input with write data. ldqs is center-aligned to write data. udqs, udqs# i/o upper byte data strobe: output with read data. edge-aligned with read data. input with write data. udqs is center-aligned to write data. v dd supply power supply: 1.35v, 1.283C1.45v operational; compatible to 1.5v operation. v ddq supply dq power supply: 1.35v, 1.283C1.45v operational; compatible with 1.5v operation. v refca supply reference voltage for control, command, and address: v refca must be maintained at all times (including self refresh) for proper device operation. v refdq supply reference voltage for data: v refdq must be maintained at all times (including self re- fresh) for proper device operation. v ss supply ground. v ssq supply dq ground: isolated on the device for improved noise immunity. zq reference external reference ball for output drive calibration: this ball is tied to an external 240 resistor (r zq ), which is tied to v ssq . nc C no connect: these balls should be left unconnected (the ball has no connection to the dram or to other balls). 2gb: x4, x8, x16 ddr3l sdram ball assignments and descriptions pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
package dimensions figure 3: 78-ball fbga C x4, x8; die rev. h, m, k (da) ball a1 id 1.2 max 0.25 min 8 0.1 ball a1 id 78x ?0.45 solder ball material: sac305 (96.5% sn, 3% ag, 0.5% cu). dimensions apply to solder balls post-reflow on ?0.35 smd ball pads. 0.8 typ 0.8 typ 9.6 ctr 10.5 0.1 0.8 0.05 0.155 1.8 ctr nonconductive overmold 0.12 a a seating plane 6.4 ctr 9 8 7 3 2 1 a b c d e f g h j k l m n note: 1. all dimensions are in millimeters. 2gb: x4, x8, x16 ddr3l sdram package dimensions pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 4: 78-ball fbga C x4, x8; die rev. d (hx) 0.8 typ 9.6 ctr 11.5 0.1 0.8 typ 6.4 ctr 9 0.1 ball a1 id ball a1 id a b c d e f g h j k l m n 1 2 3 7 8 9 78x ?0.45 dimensions apply to solder balls post-reflow on ?0.35 smd ball pads. a 0.12 a seating plane 1.1 0.1 0.25 min 1.8 ctr nonconductive overmold 0.155 notes: 1. all dimensions are in millimeters. 2. solder ball material: sac305 (96.5% sn, 3% ag, 0.5% cu). 2gb: x4, x8, x16 ddr3l sdram package dimensions pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 5: 96-ball fbga C x16; die rev. d (ha) ball a1 index dimensions apply to solder balls post-reflow on ?0.35 smd ball pads. 14 0.1 0.8 typ 1.1 0.1 12 ctr ball a1 index (covered by sr) 0.8 typ 9 0.1 0.25 min 6.4 ctr 96x ?0.45 9 8 7 3 2 1 a b c d e f g h j k l m n p r t a 0.12 a seating plane 1.8 ctr nonconductive overmold 0.155 note: 1. all dimensions are in millimeters. 2gb: x4, x8, x16 ddr3l sdram package dimensions pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
figure 6: 96-ball fbga C x16; die rev. k (jt) ball a1 id 1.2 max 0.8 typ 8 0.15 0.8 0.1 seating plane a 12 ctr 6.4 ctr 0.12 a 96x ?0.45 solder ball material: sac305 (96.5% sn, 3% ag, 0.5% cu). dimensions apply to solder balls post-reflow on ?0.35 smd ball pads. 14 0.15 ball a1 id 0.8 typ 0.25 min 9 8 7 3 2 1 a b c d e f g h j k l m n p r t note: 1. all dimensions are in millimeters. 2gb: x4, x8, x16 ddr3l sdram package dimensions pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
electrical characteristics C i dd specifications table 5: i dd maximum limits C die rev. d speed bin ddr3l-800 ddr3l-1066 ddr3l-1333 units i dd width i dd0 x4, 8 70 75 85 ma x16 85 90 100 ma i dd1 x4, 8 92 95 100 ma x16 122 125 130 ma i dd2p0 (slow) all 12 12 12 ma i dd2p1 (fast) x4, 8 22 25 30 ma x16 27 30 35 ma i dd2q all 27 30 35 ma i dd2n all 28 32 37 ma i dd2nt x4, 8 37 40 45 ma x16 52 55 60 ma i dd3p x4, 8 27 30 35 ma x16 32 35 40 ma i dd3n all 32 35 40 ma i dd4r x4 110 125 145 ma x8 125 140 160 ma x16 160 200 245 ma i dd4w x4 120 135 155 ma x8 130 145 165 ma x16 170 210 255 ma i dd5b all 185 190 200 ma i dd6 all 12 12 12 ma i dd6et all 15 15 15 ma i dd7 x4, 8 290 335 385 ma x16 330 375 425 ma i dd8 all i dd2p0 + 2ma i dd2p0 + 2ma i dd2p0 + 2ma ma 2gb: x4, x8, x16 ddr3l sdram electrical characteristics C i dd specifications pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 6: i dd maximum limits C die rev. h speed bin ddr3l-1066 ddr3l-1333 ddr3l-1600 unit i dd width i dd0 x4, 8 65 70 75 ma i dd1 x4, 8 85 90 95 ma i dd2p0 (slow) x4, 8 12 12 12 ma i dd2p1 (fast) x4, 8 27 32 37 ma i dd2q x4, 8 32 37 42 ma i dd2n x4, 8 34 38 43 ma i dd2nt x4, 8 42 47 52 ma i dd3p x4, 8 37 42 47 ma i dd3n x4, 8 42 47 52 ma i dd4r x4 110 125 140 ma x8 125 140 155 ma i dd4w x4 110 125 140 ma x8 125 140 155 ma i dd5b x4, 8 180 185 190 ma i dd6 x4, 8 12 12 12 ma i dd6et x4, 8 15 15 15 ma i dd7 x4, 8 225 240 255 ma i dd8 x4, 8 i dd2p0 + 2ma i dd2p0 + 2ma i dd2p0 + 2ma ma 2gb: x4, x8, x16 ddr3l sdram electrical characteristics C i dd specifications pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 7: i dd maximum limits C die rev. m speed bin ddr3l-1066 ddr3l-1333 ddr3l-1600 unit i dd width i dd0 x4, 8 50 55 60 ma i dd1 x4, 8 65 70 75 ma i dd2p0 (slow) x4, 8 12 12 12 ma i dd2p1 (fast) x4, 8 23 28 33 ma i dd2q x4, 8 23 28 33 ma i dd2n x4, 8 25 30 35 ma i dd2nt x4, 8 30 35 40 ma i dd3p x4, 8 37 42 47 ma i dd3n x4, 8 42 47 52 ma i dd4r x4 95 110 125 ma x8 110 125 140 ma i dd4w x4 85 100 115 ma x8 95 110 125 ma i dd5b x4, 8 180 185 190 ma i dd6 x4, 8 12 12 12 ma i dd6et x4, 8 15 15 15 ma i dd7 x4, 8 190 205 220 ma i dd8 x4, 8 i dd2p0 + 2ma i dd2p0 + 2ma i dd2p0 + 2ma ma 2gb: x4, x8, x16 ddr3l sdram electrical characteristics C i dd specifications pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 8: i dd maximum limits C die rev. k speed bin ddr3l-1066 ddr3l-1333 ddr3l-1600 ddr3-1866 units i dd width i dd0 x4, x8 36 38 39 40 ma x16 43 45 46 48 ma i dd1 x4 43 47 49 52 ma x8 46 50 52 54 ma x16 58 63 65 68 ma i dd2p0 (slow) all 12 12 12 12 ma i dd2p1 (fast) all 14 14 14 14 ma i dd2q all 20 20 20 20 ma i dd2n all 21 21 21 21 ma i dd2nt x4, x8 26 29 31 33 ma x16 30 33 34 36 ma i dd3p all 21 21 21 21 ma i dd3n x4,x8 28 30 32 34 ma x16 30 33 34 36 ma i dd4r x4 64 78 90 100 ma x8 68 82 94 104 ma x16 88 108 128 148 ma i dd4w x4 69 81 93 105 ma x8 73 85 97 108 ma x16 99 119 138 156 ma i dd5b all 107 109 110 112 ma i dd6 all 12 12 12 12 ma i dd6et all 15 15 15 15 ma i dd7 x4, 8 121 150 156 164 ma x16 152 172 195 219 ma i dd8 all i dd2p0 + 2ma i dd2p0 + 2ma i dd2p0 + 2ma i dd2p0 + 2ma ma 2gb: x4, x8, x16 ddr3l sdram electrical characteristics C i dd specifications pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
electrical specifications table 9: input/output capacitance gray-shaded cells have the same values as those in the 1.5v ddr3 data sheet capacitance parameters symbol ddr3l-800 ddr3l-1066 ddr3l-1333 ddr3l-1600 ddr3l-1866 units min max min max min max min max min max single-end i/o: dq, dm c io 1.5 2.5 1.5 2.5 1.5 2.3 1.5 2.2 1.5 2.1 pf differential i/o: dqs, dqs#, tdqs, tdqs# c io 1.5 2.5 1.5 2.5 1.5 2.3 1.5 2.2 1.5 2.1 pf inputs (ctrl, cmd,addr) c i 0.75 1.3 0.75 1.3 0.75 1.3 0.75 1.2 0.75 1.2 pf table 10: dc electrical characteristics and operating conditions C 1.35v operation all voltages are referenced to v ss parameter/condition symbol min nom max units notes supply voltage v dd 1.283 1.35 1.45 v 1, 2, 3, 4 i/o supply voltage v ddq 1.283 1.35 1.45 v 1, 2, 3, 4 notes: 1. maximum dc value may not be greater than 1.425v. the dc value is the linear average of v dd /v ddq (t) over a very long period of time (for example, 1 sec). 2. if the maximum limit is exceeded, input levels shall be governed by ddr3 specifications. 3. under these supply voltages, the device operates to this ddr3l specification. 4. once initialized for ddr3l operation, ddr3 operation may only be used if the device is in reset while v dd and v ddq are changed for ddr3 operation (see figure 7 (page 29)). table 11: dc electrical characteristics and operating conditions C 1.5v operation all voltages are referenced to v ss parameter/condition symbol min nom max units notes supply voltage v dd 1.425 1.5 1.575 v 1, 2, 3 i/o supply voltage v ddq 1.425 1.5 1.575 v 1, 2, 3 notes: 1. if the minimum limit is exceeded, input levels shall be governed by ddr3l specifications. 2. under 1.5v operation, this ddr3l device operates in accordance with the ddr3 specifi- cations under the same speed timings as defined for this device. 3. once initialized for ddr3 operation, ddr3l operation may only be used if the device is in reset while v dd and v ddq are changed for ddr3l operation (see figure 7 (page 29)). 2gb: x4, x8, x16 ddr3l sdram electrical specifications pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 12: input switching conditions C command and address parameter/condition symbol ddr3l-800/1066 ddr3l-1333/1600 ddr3l-1866 units input high ac voltage: logic 1 v ih(ac160)min 1 160 160 C mv input high ac voltage: logic 1 v ih(ac135)min 1 135 135 135 mv input high ac voltage: logic 1 v ih(ac125)min 1 C C 125 mv input high dc voltage: logic 1 v ih(dc90)min 90 90 90 mv input low dc voltage: logic 0 v il(dc90)min C90 C90 C90 mv input low ac voltage: logic 0 v il(ac125)min 1 C C C125 mv input low ac voltage: logic 0 v il(ac135)min 1 C135 C135 C135 mv input low ac voltage: logic 0 v il(ac160)min 1 C160 C160 C mv note: 1. when two v ih(ac) values (and two corresponding v il(ac) values) are listed for a specific speed bin, the user may choose either value for the input ac level. whichever value is used, the associated setup time for that ac level must also be used. additionally, one v ih(ac) value may be used for address/command inputs and the other v ih(ac) value may be used for data inputs. for example, for ddr3l-800, two input ac levels are defined: v ih(ac160),min and v ih(ac135),min (corresponding v il(ac160),min and v il(ac135),min ). for ddrl-800, the address/ command inputs must use either v ih(ac160),min with t is(ac160) of 215ps or v ih(ac135),min with t is(ac135) of 365ps; independently, the data inputs may use either v ih(ac160),min or v ih(ac135),min . table 13: input switching conditions C dq and dm parameter/condition symbol ddr3l-800/1066 ddr3l-1333/1600 ddr3l-1866 units input high ac voltage: logic 1 v ih(ac160)min 1 160 160 C mv input high ac voltage: logic 1 v ih(ac135)min 1 135 135 135 mv input high ac voltage: logic 1 v ih(ac125)min 1 C C 130 mv input high dc voltage: logic 1 v ih(dc90)min 90 90 90 mv input low dc voltage: logic 0 v il(dc90)min C90 C90 C90 mv input low ac voltage: logic 0 v il(ac125)min 1 C C C130 mv input low ac voltage: logic 0 v il(ac135)min 1 C135 C135 C135 mv input low ac voltage: logic 0 v il(ac160)min 1 C160 C160 C mv note: 1. when two v ih(ac) values (and two corresponding v il(ac) values) are listed for a specific speed bin, the user may choose either value for the input ac level. whichever value is used, the associated setup time for that ac level must also be used. additionally, one v ih(ac) value may be used for address/command inputs and the other v ih(ac) value may be used for data inputs. for example, for ddr3l-800, two input ac levels are defined: v ih(ac160),min and v ih(ac135),min (corresponding v il(ac160),min and v il(ac135),min ). for ddrl-800, the data in- puts must use either v ih(ac160),min with t is(ac160) of 90ps or v ih(ac135),min with t is(ac135) of 140ps; independently, the address/command inputs may use either v ih(ac160),min or v ih(ac135),min . 2gb: x4, x8, x16 ddr3l sdram electrical specifications pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 18 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 14: differential input operating conditions (ck, ck# and dqs, dqs#) parameter/condition symbol min max units differential input logic high C slew v ih,diff(ac)slew 180 n/a mv differential input logic low C slew v il,diff(ac)slew n/a C180 mv differential input logic high v ih,diff(ac) 2 (v ih(ac) - v ref ) v dd /v ddq mv differential input logic low v il,diff(ac) v ss /v ssq 2 (v il(ac) - v ref ) mv single-ended high level for strobes v seh v ddq /2 + 160 v ddq mv single-ended high level for ck, ck# v dd /2 + 160 v dd mv single-ended low level for strobes v sel v ssq v ddq /2 - 160 mv single-ended low level for ck, ck# v ss v dd /2 - 160 mv table 15: minimum required time t dvac for ck/ck#, dqs/dqs# differential for ac ringback slew rate (v/ns) ddr3l-800/1066/1333/1600 ddr3l-1866 t dvac at 320mv (ps) t dvac at 270mv (ps) t dvac at 270mv (ps) t dvac at 250mv (ps) t dvac at 260mv (ps) >4.0 189 201 163 168 176 4.0 189 201 163 168 176 3.0 162 179 140 147 154 2.0 109 134 95 105 111 1.8 91 119 80 91 97 1.6 69 100 62 74 78 1.4 40 76 37 52 55 1.2 note1 44 5 22 24 1.0 note1 note1 note1 note1 note1 <1.0 note1 note1 note1 note1 note1 note: 1. rising input signal shall become equal to or greater than vih(ac) level and falling input signal shall become equal to or less than vil(ac) level. 2gb: x4, x8, x16 ddr3l sdram electrical specifications pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 19 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 16: r tt effective impedance gray-shaded cells have the same values as those in the 1.5v ddr3 data sheet mr1 [9, 6, 2] r tt resistor v out min nom max units 0, 1, 0 120 r tt,120pd240 0.2 v ddq 0.6 1.0 1.15 rzq/1 0.5 v ddq 0.9 1.0 1.15 rzq/1 0.8 v ddq 0.9 1.0 1.45 rzq/1 r tt,120pu240 0.2 v ddq 0.9 1.0 1.45 rzq/1 0.5 v ddq 0.9 1.0 1.15 rzq/1 0.8 v ddq 0.6 1.0 1.15 rzq/1 120 v il(ac) to v ih(ac) 0.9 1.0 1.65 rzq/2 0, 0, 1 60 r tt,60pd120 0.2 v ddq 0.6 1.0 1.15 rzq/2 0.5 v ddq 0.9 1.0 1.15 rzq/2 0.8 v ddq 0.9 1.0 1.45 rzq/2 r tt,60pu120 0.2 v ddq 0.9 1.0 1.45 rzq/2 0.5 v ddq 0.9 1.0 1.15 rzq/2 0.8 v ddq 0.6 1.0 1.15 rzq/2 60 v il(ac) to v ih(ac) 0.9 1.0 1.65 rzq/4 0, 1, 1 40 r tt,40pd80 0.2 v ddq 0.6 1.0 1.15 rzq/3 0.5 v ddq 0.9 1.0 1.15 rzq/3 0.8 v ddq 0.9 1.0 1.45 rzq/3 r tt,40pu80 0.2 v ddq 0.9 1.0 1.45 rzq/3 0.5 v ddq 0.9 1.0 1.15 rzq/3 0.8 v ddq 0.6 1.0 1.15 rzq/3 40 v il(ac) to v ih(ac) 0.9 1.0 1.65 rzq/6 1, 0, 1 30 r tt,30pd60 0.2 v ddq 0.6 1.0 1.15 rzq/4 0.5 v ddq 0.9 1.0 1.15 rzq/4 0.8 v ddq 0.9 1.0 1.45 rzq/4 r tt,30pu60 0.2 v ddq 0.9 1.0 1.45 rzq/4 0.5 v ddq 0.9 1.0 1.15 rzq/4 0.8 v ddq 0.6 1.0 1.15 rzq/4 30 v il(ac) to v ih(ac) 0.9 1.0 1.65 rzq/8 1, 0, 0 20 r tt,20pd40 0.2 v ddq 0.6 1.0 1.15 rzq/6 0.5 v ddq 0.9 1.0 1.15 rzq/6 0.8 v ddq 0.9 1.0 1.45 rzq/6 r tt,20pu40 0.2 v ddq 0.9 1.0 1.45 rzq/6 0.5 v ddq 0.9 1.0 1.15 rzq/6 0.8 v ddq 0.6 1.0 1.15 rzq/6 20 v il(ac) to v ih(ac) 0.9 1.0 1.65 rzq/12 2gb: x4, x8, x16 ddr3l sdram electrical specifications pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 20 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 17: reference settings for odt timing measurements gray-shaded cells have the same values as those in the 1.5v ddr3 data sheet measured parameter r tt,nom setting r tt(wr) setting v sw1 v sw2 t aon rzq/4 (60 ) n/a 50mv 100mv rzq/12 (20 ) n/a 100mv 200mv t aof rzq/4 (60 ) n/a 50mv 100mv rzq/12 (20 ) n/a 100mv 200mv t aonpd rzq/4 (60 ) n/a 50mv 100mv rzq/12 (20 ) n/a 100mv 200mv t aofpd rzq/4 (60 ) n/a 50mv 100mv rzq/12 (20 ) n/a 100mv 200mv t adc rzq/12 (20 ) rzq/2 (20 ) 200mv 250mv table 18: 34 driver impedance characteristics gray-shaded cells have the same values as those in the 1.5v ddr3 data sheet mr1 [5, 1] r on resistor v out min nom max 1 units 0, 1 34.3 r on,34pd 0.2 v ddq 0.6 1.0 1.15 rzq/7 0.5 v ddq 0.9 1.0 1.15 rzq/7 0.8 v ddq 0.9 1.0 1.45 rzq/7 r on,34pu 0.2 v ddq 0.9 1.0 1.45 rzq/7 0.5 v ddq 0.9 1.0 1.15 rzq/7 0.8 v ddq 0.6 1.0 1.15 rzq/7 pull-up/pull-down mismatch (mm pupd ) v il(ac) to v ih(ac) C10 n/a 10 % note: 1. a larger maximum limit will result in slightly lower minimum currents. table 19: 40 driver impedance characteristics gray-shaded cells have the same values as those in the 1.5v ddr3 data sheet mr1 [5, 1] r on resistor v out min nom max 1 units 0, 0 40 r on,40pd 0.2 v ddq 0.6 1.0 1.15 rzq/6 0.5 v ddq 0.9 1.0 1.15 rzq/6 0.8 v ddq 0.9 1.0 1.45 rzq/6 r on,40pu 0.2 v ddq 0.9 1.0 1.45 rzq/6 0.5 v ddq 0.9 1.0 1.15 rzq/6 0.8 v ddq 0.6 1.0 1.15 rzq/6 pull-up/pull-down mismatch (mm pupd ) v il(ac) to v ih(ac) C10 n/a 10 % note: 1. a larger maximum limit will result in slightly lower minimum currents. 2gb: x4, x8, x16 ddr3l sdram electrical specifications pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 21 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 20: single-ended output driver characteristics gray-shaded cells have the same values as those in the 1.5v ddr3 data sheet parameter/condition symbol min max units output slew rate: single-ended; for rising and falling edges, measure between v ol(ac) = v ref - 0.09 v ddq and v oh(ac) = v ref + 0.09 v ddq srq se 1.75 6 v/ns table 21: differential output driver characteristics gray-shaded cells have the same values as those in the 1.5v ddr3 data sheet parameter/condition symbol min max units output slew rate: differential; for rising and falling edges, measure between v ol,diff(ac) = C0.18 v ddq and v oh,diff(ac) = 0.18 v ddq srq diff 3.5 12 v/ns output differential crosspoint voltage v ox(ac) v ref - 135 v ref + 135 mv table 22: electrical characteristics and ac operating conditions note 1 applies to base timing specifications parameter symbol ddr3l-800 ddr3l-1066 ddr3l-1333 ddr3l-1600 ddr3l-1866 units min max min max min max min max min max dq input timing data setup time to dqs, dqs# base (specification) t ds (ac160) 90 C 40 C n/a C n/a C n/a C ps v ref @ 1 v/ns 250 C 200 C n/a C n/a C n/a C ps data setup time to dqs, dqs# base (specification) t ds (ac135) 140 C 90 C 45 C 25 C n/a C ps v ref @ 1 v/ns 275 C 225 C 180 C 160 C n/a C ps data hold time from dqs, dqs# base (specification) t dh (dc90) 160 C 110 C 75 C 55 C n/a C ps v ref @ 1 v/ns 250 C 200 C 165 C 145 C n/a C ps data setup time to dqs, dqs# base (specification) t ds (ac130) n/a C n/a C n/a C n/a C 70 C ps v ref @ 2 v/ns n/a C n/a C n/a C n/a C 135 C ps data hold time from dqs, dqs# base (specification) t dh (dc90) n/a C n/a C n/a C n/a C 75 C ps v ref @ 2 v/ns n/a C n/a C n/a C n/a C 110 C ps command and address timing ctrl, cmd, addr setup to ck, ck# base (specification) t is (ac160) 215 C 140 C 80 C 60 C n/a C ps v ref @ 1 v/ns 375 C 300 C 240 C 220 C n/a C ps ctrl, cmd, addr setup to ck, ck# base (specification) t is (ac135) 365 C 290 C 205 C 185 C 65 C ps v ref @ 1 v/ns 500 C 425 C 340 C 320 C 200 C ps 2gb: x4, x8, x16 ddr3l sdram electrical specifications pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 22 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 22: electrical characteristics and ac operating conditions (continued) note 1 applies to base timing specifications parameter symbol ddr3l-800 ddr3l-1066 ddr3l-1333 ddr3l-1600 ddr3l-1866 units min max min max min max min max min max ctrl, cmd, addr setup to ck, ck# base (specification) t is (ac125) n/a C n/a C n/a C n/a C 150 C ps v ref @ 1 v/ns n/a C n/a C n/a C n/a C 275 C ps ctrl, cmd, addr hold from ck, ck# base (specification) t ih (dc90) 285 C 210 C 150 C 130 C 110 C ps v ref @ 1 v/ns 375 C 300 C 240 C 220 C 200 C ps notes: 1. when two v ih(ac) values (and two corresponding v il(ac) values) are listed for a specific speed bin, the user may choose either value for the input ac level. whichever value is used, the associated setup time for that ac level must also be used. additionally, one v ih(ac) value may be used for address/command inputs and the other v ih(ac) value may be used for data inputs. for example, for ddr3-800, two input ac levels are defined: v ih(ac160),min and v ih(ac135),min (corresponding v il(ac160),min and v il(ac135),min ). for ddr3-800, the address/ command inputs must use either v ih(ac160),min with t is(ac160) of 215ps or v ih(ac135),min with t is(ac135) of 365ps; independently, the data inputs must use either v ih(ac160),min with t ds(ac160) of 90ps or v ih(ac135),min with t ds(ac135) of 140ps. 2. when dq single-ended slew rate is 1v/ns, the dqs differential slew rate is 2v/ns; when dq single-ended slew rate is 2v/ns, the dqs differential slew rate is 4v/ns; table 23: derating values for t is/ t ih C ac160/dc90-based t is, t ih derating (ps) C ac/dc-based cmd/addr slew rate v/ns ck, ck# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih 2.0 80 45 80 45 80 45 88 53 96 61 104 69 112 79 120 95 1.5 53 30 53 30 53 30 61 38 69 46 77 54 85 64 93 80 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 C1 C3 C1 C3 C1 C3 7 5 15 13 23 21 31 31 39 47 0.8 C3 C8 C3 C8 C3 C8 5 1 13 9 21 17 29 27 37 43 0.7 C5 C13 C5 C13 C5 C13 3 C5 11 3 19 11 27 21 35 37 0.6 C8 C20 C8 C20 C8 C20 0 C12 8 C4 16 4 24 14 32 30 0.5 C20 C30 C20 C30 C20 C30 C12 C22 C4 C14 4 C6 12 4 20 20 0.4 C40 C45 C40 C45 C40 C45 C32 C37 C24 C29 C16 C21 C8 C11 0 5 2gb: x4, x8, x16 ddr3l sdram electrical specifications pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 23 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 24: derating values for t is/ t ih C ac135/dc90-based t is, t ih derating (ps) C ac/dc-based cmd/addr slew rate v/ns ck, ck# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih 2.0 68 45 68 45 68 45 76 53 84 61 92 69 100 79 108 95 1.5 45 30 45 30 45 30 53 38 61 46 69 54 77 64 85 80 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 2 C3 2 C3 2 C3 10 5 18 13 26 21 34 31 42 47 0.8 3 C8 3 C8 3 C8 11 1 19 9 27 17 35 27 43 43 0.7 6 C13 6 C13 6 C13 14 C5 22 3 30 11 38 21 46 37 0.6 9 C20 9 C20 9 C20 17 C12 25 C4 33 4 41 14 49 30 0.5 5 C30 5 C30 5 C30 13 C22 21 C14 29 C6 37 4 45 20 0.4 C3 C45 C3 C45 C3 C45 6 C37 14 C29 22 C21 30 C11 38 5 table 25: derating values for t is/ t ih C ac125/dc90-based t is, t ih derating (ps) C ac/dc-based cmd/addr slew rate v/ns ck, ck# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih 2.0 63 45 63 45 63 45 71 53 79 61 87 69 95 79 103 95 1.5 42 30 42 30 42 30 50 38 58 46 66 54 74 64 82 80 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 3 C3 3 C3 3 C3 11 5 19 13 27 21 35 31 43 47 0.8 6 C8 6 C8 6 C8 14 1 22 9 30 17 38 27 46 43 0.7 10 C13 10 C13 10 C13 18 C5 26 3 34 11 42 21 50 37 0.6 16 C20 16 C20 16 C20 24 C12 32 C4 40 4 48 14 56 30 0.5 15 C30 15 C30 15 C30 23 C22 31 C14 39 C6 47 4 55 20 0.4 13 C45 13 C45 13 C45 21 C37 29 C29 37 C21 45 C11 53 5 2gb: x4, x8, x16 ddr3l sdram electrical specifications pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 24 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 26: minimum required time t vac above v ih(ac) (below v il[ac] ) for valid add/cmd transition slew rate (v/ns) ddr3l-800/1066/1333/1600 ddr3l-1866 t vac at 160mv (ps) t vac at 135mv (ps) t vac at 135mv (ps) t vac at 125mv (ps) >2.0 70 209 200 205 2.0 53 198 200 205 1.5 47 194 178 184 1.0 35 186 133 143 0.9 31 184 118 129 0.8 26 181 99 111 0.7 20 177 75 89 0.6 12 171 43 59 0.5 note 1 164 note 1 18 <0.5 note 1 164 note 1 18 note: 1. rising input signal shall become equal to or greater than vih(ac) level and falling input signal shall become equal to or less than vil(ac) level. table 27: derating values for t ds/ t dh C ac160/dc90-based t ds, t dh derating (ps) C ac/dc-based dq slew rate v/ns dqs, dqs# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh 2.0 80 45 80 45 80 45 1.5 53 30 53 30 53 30 61 38 1.0 0 0 0 0 0 0 8 8 16 16 0.9 C1 C3 C1 C3 7 5 15 13 23 21 0.8 C3 C8 5 1 13 9 21 17 29 27 0.7 C3 C5 11 3 19 11 27 21 35 37 0.6 8 C4 16 4 24 14 32 30 0.5 4 6 12 4 20 20 0.4 C8 C11 0 5 2gb: x4, x8, x16 ddr3l sdram electrical specifications pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 25 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 28: derating values for t ds/ t dh C ac135/dc90-based t ds, t dh derating (ps) C ac/dc-based dq slew rate v/ns dqs, dqs# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh 2.0 68 45 68 45 68 45 1.5 45 30 45 30 45 30 53 38 1.0 0 0 0 0 0 0 8 8 16 16 0.9 2 C3 2 C3 10 5 18 13 26 21 0.8 3 C8 11 1 19 9 27 17 35 27 0.7 14 C5 22 3 30 11 38 21 46 37 0.6 25 C4 33 4 41 14 49 30 0.5 39 C6 37 4 45 20 0.4 30 C11 38 5 2gb: x4, x8, x16 ddr3l sdram electrical specifications pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 26 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 29: derating values for t ds/ t dh C ac130/dc100-based at 2v/ns shaded cells indicate slew rate combinations not supported t ds, t dh derating (ps) C ac/dc-based dq slew rate v/ns dqs, dqs# differential slew rate 8.0 v/ns 7.0 v/ns 6.0 v/ns 5.0 v/ns 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh 4.0 33 23 33 23 33 23 3.5 28 19 28 19 28 19 28 19 3.0 22 15 22 15 22 15 22 15 22 15 2.5 13 9 13 9 13 9 13 9 13 9 2.0 0 0 0 0 0 0 0 0 0 0 1.5 C22 C15 C22 C15 C22 C15 C22 C15 C14 C7 1.0 C65 C45 C65 C45 C65 C45 C57 C37 C49 C29 0.9 C62 C48 C62 C48 C54 C40 C46 C32 C38 C24 0.8 C61 C53 C53 C45 C45 C37 C37 C29 C29 C19 0.7 C49 C50 C41 -42 C33 C34 C25 C24 C17 C8 0.6 C37 -49 C29 C41 C21 C31 C13 C15 0.5 C31 C51 C23 C41 C15 C25 0.4 C28 C56 C20 C40 2gb: x4, x8, x16 ddr3l sdram electrical specifications pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 27 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
table 30: minimum required time t vac above v ih(ac) (below v il(ac) ) for valid dqtransition slew rate (v/ns) t vac at 160mv (ps) t vac at 135mv (ps) t vac at 130mv (ps) >2.0 165 113 95 2.0 165 113 95 1.5 138 90 73 1.0 85 45 30 0.9 67 30 16 0.8 45 11 note1 0.7 16 note1 C 0.6 note1 note1 C 0.5 note1 note1 C <0.5 note1 note1 C note: 1. rising input signal shall become equal to or greater than vih(ac) level and falling input signal shall become equal to or less than vil(ac) level. initialization if the sdram is powered up and initialized for the 1.35v operating voltage range, volt- age can be increased to the 1.5v operating range provided that: ? just prior to increasing the 1.35v operating voltages, no further commands are issued, other than nops or command inhibits, and all banks are in the precharge state. ? the 1.5v operating voltages are stable prior to issuing new commands, other than nops or command inhibits. ? the dll is reset and relocked after the 1.5v operating voltages are stable and prior to any read command. ? the zq calibration is performed. t zqinit must be satisfied after the 1.5v operating voltages are stable and prior to any read command. if the sdram is powered up and initialized for the 1.5v operating voltage range, voltage can be reduced to the 1.35v operation range provided that: ? just prior to reducing the 1.5v operating voltages, no further commands are issued, other than nops or command inhibits, and all banks are in the precharge state. ? the 1.35v operating voltages are stable prior to issuing new commands, other than nops or command inhibits. ? the dll is reset and relocked after the 1.35v operating voltages are stable and prior to any read command. ? the zq calibration is performed. t zqinit must be satisfied after the 1.35v operating voltages are stable and prior to any read command. 2gb: x4, x8, x16 ddr3l sdram initialization pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 28 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/
v dd voltage switching after the ddr3l dram is powered up and initialized, the power supply can be altered between the ddr3l and ddr3 levels, provided the sequence in figure 7 is maintained. figure 7: v dd voltage switching ( ) ( ) ( ) ( ) cke r tt ba ( ) ( ) ( ) ( ) ck, ck# command note 1 note 1 ( ) ( ) ( ) ( ) td tc tg dont care ( ) ( ) ( ) ( ) ( ) ( ) t is odt ( ) ( ) ( ) ( ) th t mrd t mod ( ) ( ) ( ) ( ) mrs mrs ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t mrd t mrd ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) mrs mr0 mr1 mr3 mrs mr2 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ti tj tk ( ) ( ) ( ) ( ) reset# ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t = 500s ( ) ( ) ( ) ( ) ( ) ( ) te ta tb tf ( ) ( ) ( ) ( ) zqcl ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t is static low in case r t t ,nom is enabled at time tg, otherwise static high or low ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t is t is t xpr ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) time break t min = 10ns t min = 10ns t min = 10ns t min = 200s t cksrx v dd , v ddq (ddr3) ( ) ( ) ( ) ( ) t dllk ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t zqinit ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) v dd , v ddq (ddr3l) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) valid valid valid valid ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) note: 1. from time point td until tk, nop or des commands must be applied between mrs and zqcl commands. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 2gb: x4, x8, x16 ddr3l sdram initialization pdf: 09005aef83ed2952 2gb_1_35v_ddr3l.pdf - rev. g 2/12 en 29 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. www.datasheet.co.kr datasheet pdf - http://www..net/

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